The present invention relates to integrated circuit devices, and more particularly, to integrated circuit devices including a cell pad contact hole and methods for forming the same.
Integrated circuit (semiconductor) devices are widely used in consumer and commercial applications. Such devices may include cell pad contact holes. Two kinds of known failures in such devices result from an increase and a decrease in the resistance of the cell pad contact hole detected, for example, during Electrical Die Sorting (EDS) testing of the integrated circuit device.
In some cases, a cell pad contact hole may be formed that is smaller than the size specified by a design rule for the integrated circuit device's manufacturing process. As a result, the cell pad contact hole may exhibit a very high resistance. Furthermore, the voltage level of data transmitted from a peripheral circuit region through the cell pad contact hole may be reduced in proportion to the amount of excess resistance of the cell pad contact hole. The integrated circuit device may then have a refresh failure as a result of a reduction of a sensing margin of the device from the voltage drop of the cell pad contact hole.
In other cases, the cell pad contact hole may be formed with a larger size than is required by the design rule. The resulting cell pad contact hole may exhibit a very low resistance. As a result, the high voltage level of data transmitted from the peripheral circuit region through the cell pad contact hole may affect (leak into) an adjacent channel region under a gate of the integrated circuit device because the region between the cell pad contact and the gate may be insufficient given the size of the cell pad contact region. The integrated circuit device may then have a refresh failure as a result of a reduction of sensing margin caused by the voltage leak.
Examples of known methods for fabrication of a cell pad contact hole are described in U.S. Pat. No. 6,204,134 (“the '134 patent”) entitled “Method for fabricating a self aligned contact plug,” which is incorporated herein by reference.
As described in the '134, the process begins by providing a substrate structure, having a first gate structure and a second gate structure thereon and having a contact area between the first gate structure and the second gate structure. An interlevel dielectric layer is formed over the first gate structure and the second gate structure. The interlevel dielectric layer is patterned to form a self aligned contact opening over the contact area. Impurity ions are implanted into the substrate structure through the self aligned contact opening to form source and drain regions. In the key steps, a high temperature polysilicon film is formed over the source and drain regions, and a furnace doped polysilicon layer is formed over the high temperature polysilicon film (forming a pad poly film of the cell pad contact hole). The furnace doped polysilicon layer and the high temperature polysilicon film are planarized to form a polysilicon self aligned contact plug. This process may reduce the resistance a pad poly film of the cell pad contact hole formed on a cell array area and decrease a leak current from a junction formed around the cell pad contact hole, which may improve design performance of the integrated circuit device.
The first poly film of the pad poly film may be an undoped poly film for curing damage caused by forming the cell pad contact hole on the semiconductor substrate. The second poly film may be a doped poly film to reduce the resistance of the pad poly film of the cell pad contact hole.
The ion implanting process and the key process may, therefore, reduce contact resistance between the pad poly film and the semiconductor substrate. However, the effective channel length of a gate adjacent to the cell pad contact hole may be reduced because ions and/or dopants from the two processes may be diffused into the semiconductor substrate, which may cause a dynamic refresh fail in the semiconductor device.
A conventional semiconductor device having a pad poly film will now be further described with reference to FIG. 1. FIG. 1 is a cross sectional view of semiconductor substrate including a conventional pad poly film. As shown in FIG. 1, a device isolating film 15 is formed on a predetermined region of the semiconductor substrate 10. A gate oxide film (not shown) is disposed on the semiconductor substrate 10 and the device isolating film 15. AND gates 28 are formed on the gate oxide film. Gates 28 are composed of a poly film 20, a Wsi film 23 and a first nitride film 26 sequentially stacked on the gate oxide film. N-type source/drain regions 27 are formed in the semiconductor substrate 10 overlapping with the gates 28. Gate spacers 29 cover the sidewalls of the gates 28 using a second nitride film (not shown).
An insulating film 32 is formed to planarize the semiconductor substrate 10. The insulating film 32 is etched to expose the semiconductor substrate 10 to form a cell pad contact hole 35, wherein the cell pad contact hole 35 is self-aligned to the gates 28 and the gate spacers 29. Subsequently, a third nitride film (not shown) is formed on the top surface of the insulating film 32 and in the cell pad contact hole 35 to form a spacer 38 on the sidewall of the cell pad contact hole 35.
A pad poly film 40 is formed in the cell pad contact hole 35 and on the insulating film 32 and etched back to expose the top surface of the insulating film 32. As a result, the cell pad contact hole 35 is filled with the pad poly film 40.
At this time, the semiconductor device structure may include residue (not shown) of the pad poly film 40 in the regions around the cell pad contact hole 35. Such residue may be subsequently removed with an additional cleaning step, wherein the spacer 38 may act as a buffer film to reduce or prevent damage to the insulating film 32 during the additional cleaning step.
However, using this process, the cell pad contact hole 35 is reduced to a contact having a diameter 1L as a result of formation of the spacer 38. As shown in FIG. 1, the diameter 1L corresponds to a width of the pad poly film 40 contacting the semiconductor substrate 10. Thus, the pad poly film 40 filling the cell pad contact hole 35 has a higher resistance than it would without the spacers 38. When the pad poly film 40 is filled in the cell pad contact hole 35, the spacer 38 does not act as a conductive film.
The resistance of the pad poly film 40 filling the cell pad contact hole 35 may be decreased by forming an impurity region 39 in the substrate 10 through an ion implantation process through the cell pad contact hole 35. However the impurity region 39 may help diffuse ions into adjacent discriminate devices, so that the gates 28 have an effective channel length 2L. The effective channel length 2L can cause a punchthrough between N-type source/drain regions 27 overlapping with the gates 28. As a result, the semiconductor device structure may result in poor refresh operation and deteriorate a performance characteristic of the semiconductor device.